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Like SRA, except a 0 is put into bit 7. The bits are all shifted right, with bit 0 put into the carry flag.
SRL A SRL B SRL C SRL D SRL E SRL H SRL L SRL (HL) SRL (IX+d) SRL (IY+d)
S, H, and N flags reset, Z if result is zero, P/V set if parity is even, C from bit 0.
r denotes 8-bit register.