Z80:Opcode Reference Chart

This is an opcode reference chart for on-calculator programming and/or size optimizations.

Rows are first nibble, columns are second.

Primary

	0	1	2	3	4	5	6	7	8	9	A	B	C	D	E	F
0	nop	ld bc,xx	ld (bc),a	inc bc	inc b	dec b	ld b,x	rlca	ex af,af'	add hl,bc	ld a,(bc)	dec bc	inc c	dec c	ld c,x	rrca
1	djnz x	ld de,xx	ld (de),a	inc de	inc d	dec d	ld d,x	rla	jr x	add hl,de	ld a,(de)	dec de	inc e	dec e	ld e,x	rra
2	jr nz,x	ld hl,xx	ld (xx),hl	inc hl	inc h	dec h	ld h,x	daa	jr z,x	add hl,hl	ld hl,(xx)	dec hl	inc l	dec l	ld l,x	cpl
3	jr nc,x	ld sp,xx	ld (xx),a	inc sp	inc (hl)	dec (hl)	ld (hl),x	scf	jr c,x	add hl,sp	ld a,(xx)	dec sp	inc a	dec a	ld a,x	ccf
4	ld b,b	ld b,c	ld b,d	ld b,e	ld b,h	ld b,l	ld b,(hl)	ld b,a	ld c,b	ld c,c	ld c,d	ld c,e	ld c,h	ld c,l	ld c,(hl)	ld c,a
5	ld d,b	ld d,c	ld d,d	ld d,e	ld d,h	ld d,l	ld d,(hl)	ld d,a	ld e,b	ld e,c	ld e,d	ld e,e	ld e,h	ld e,l	ld e,(hl)	ld e,a
6	ld h,b	ld h,c	ld h,d	ld h,e	ld h,h	ld h,l	ld h,(hl)	ld h,a	ld l,b	ld l,c	ld l,d	ld l,e	ld l,h	ld l,l	ld l,(hl)	ld l,a
7	ld (hl),b	ld (hl),c	ld (hl),d	ld (hl),e	ld (hl),h	ld (hl),l	halt	ld (hl),a	ld a,b	ld a,c	ld a,d	ld a,e	ld a,h	ld a,l	ld a,(hl)	ld a,a
8	add a,b	add a,c	add a,d	add a,e	add a,h	add a,l	add a,(hl)	add a,a	adc a,b	adc a,c	adc a,d	adc a,e	adc a,h	adc a,l	adc a,(hl)	adc a,a
9	sub b	sub c	sub d	sub e	sub h	sub l	sub (hl)	sub a	sbc a,b	sbc a,c	sbc a,d	sbc a,e	sbc a,h	sbc a,l	sbc a,(hl)	sbc a,a
A	and b	and c	and d	and e	and h	and l	and (hl)	and a	xor b	xor c	xor d	xor e	xor h	xor l	xor (hl)	xor a
B	or b	or c	or d	or e	or h	or l	or (hl)	or a	cp b	cp c	cp d	cp e	cp h	cp l	cp (hl)	cp a
C	ret nz	pop bc	jp nz,xx	jp xx	call nz,xx	push bc	add a,x	rst 00h	ret z	ret	jp z,xx	xxBITxx	call z,xx	call xx	adc a,x	rst 08h
D	ret nc	pop de	jp nc,xx	out (x),a	call nc,xx	push de	sub x	rst 10h	ret c	exx	jp c,xx	in a,(x)	call c,xx	xxIXxx	sbc a,x	rst 18h
E	ret po	pop hl	jp po,xx	ex (sp),hl	call po,xx	push hl	and x	rst 20h	ret pe	jp (hl)	jp pe,xx	ex de,hl	call pe,xx	xx80xx	xor x	rst 28h
F	ret p	pop af	jp p,xx	di	call p,xx	push af	or x	rst 30h	ret m	ld sp,hl	jp m,xx	ei	call m,xx	xxIYxx	cp x	rst 38h

xx80xx (ED)

	0	1	2	3	4	5	6	7	8	9	A	B	C	D	E	F
4	in b,(c)	out (c),b	sbc hl,bc	ld (xx),bc	neg	retn	im 0	ld i,a	in c,(c)	out (c),c	adc hl,bc	ld bc,(xx)	neg	reti		ld r,a
5	in d,(c)	out (c),d	sbc hl,de	ld (xx),de	neg	retn	im 1	ld a,i	in e,(c)	out (c),e	adc hl,de	ld de,(xx)	neg	retn	im 2	ld a,r
6	in h,(c)	out (c),h	sbc hl,hl	ld (xx),hl	neg	retn		rrd	in l,(c)	out (c),l	adc hl,hl	ld hl,(xx)	neg	retn		rld
7	in f,(c)	out (c),f	sbc hl,sp	ld (xx),sp	neg	retn			in a,(c)	out (c),a	adc hl,sp	ld sp,(xx)	neg	reti
A	ldi	cpi	ini	outi					ldd	cpd	ind	outd
B	ldir	cpir	inir	otir					lddr	cpdr	indr	otdr

xxBITxx (CB)

Blank spaces or spaces not listed function like NOP.

	0	1	2	3	4	5	6	7	8	9	A	B	C	D	E	F
0	rlc b	rlc c	rlc d	rlc e	rlc h	rlc l	rlc (hl)	rlc a	rrc b	rrc c	rrc d	rrc e	rrc h	rrc l	rrc (hl)	rrc a
1	rl b	rl c	rl d	rl e	rl h	rl l	rl (hl)	rl a	rr b	rr c	rr d	rr e	rr h	rr l	rr (hl)	rr a
2	sla b	sla c	sla d	sla e	sla h	sla l	sla (hl)	sla a	sra b	sra c	sra d	sra e	sra h	sra l	sra (hl)	sra a
3	sll b	sll c	sll d	sll e	sll h	sll l	sll (hl)	sll a	srl b	srl c	srl d	srl e	srl h	srl l	srl (hl)	srl a
4	bit 0,b	bit 0,c	bit 0,d	bit 0,e	bit 0,h	bit 0,l	bit 0,(hl)	bit 0,a	bit 1,b	bit 1,c	bit 1,d	bit 1,e	bit 1,h	bit 1,l	bit 1,(hl)	bit 1,a
5	bit 2,b	bit 2,c	bit 2,d	bit 2,e	bit 2,h	bit 2,l	bit 2,(hl)	bit 2,a	bit 3,b	bit 3,c	bit 3,d	bit 3,e	bit 3,h	bit 3,l	bit 3,(hl)	bit 3,a
6	bit 4,b	bit 4,c	bit 4,d	bit 4,e	bit 4,h	bit 4,l	bit 4,(hl)	bit 4,a	bit 5,b	bit 5,c	bit 5,d	bit 5,e	bit 5,h	bit 5,l	bit 5,(hl)	bit 5,a
7	bit 6,b	bit 6,c	bit 6,d	bit 6,e	bit 6,h	bit 6,l	bit 6,(hl)	bit 6,a	bit 7,b	bit 7,c	bit 7,d	bit 7,e	bit 7,h	bit 7,l	bit 7,(hl)	bit 7,a
8	res 0,b	res 0,c	res 0,d	res 0,e	res 0,h	res 0,l	res 0,(hl)	res 0,a	res 1,b	res 1,c	res 1,d	res 1,e	res 1,h	res 1,l	res 1,(hl)	res 1,a
9	res 2,b	res 2,c	res 2,d	res 2,e	res 2,h	res 2,l	res 2,(hl)	res 2,a	res 3,b	res 3,c	res 3,d	res 3,e	res 3,h	res 3,l	res 3,(hl)	res 3,a
A	res 4,b	res 4,c	res 4,d	res 4,e	res 4,h	res 4,l	res 4,(hl)	res 4,a	res 5,b	res 5,c	res 5,d	res 5,e	res 5,h	res 5,l	res 5,(hl)	res 5,a
B	res 6,b	res 6,c	res 6,d	res 6,e	res 6,h	res 6,l	res 6,(hl)	res 6,a	res 7,b	res 7,c	res 7,d	res 7,e	res 7,h	res 7,l	res 7,(hl)	res 7,a
C	set 0,b	set 0,c	set 0,d	set 0,e	set 0,h	set 0,l	set 0,(hl)	set 0,a	set 1,b	set 1,c	set 1,d	set 1,e	set 1,h	set 1,l	set 1,(hl)	set 1,a
D	set 2,b	set 2,c	set 2,d	set 2,e	set 2,h	set 2,l	set 2,(hl)	set 2,a	set 3,b	set 3,c	set 3,d	set 3,e	set 3,h	set 3,l	set 3,(hl)	set 3,a
E	set 4,b	set 4,c	set 4,d	set 4,e	set 4,h	set 4,l	set 4,(hl)	set 4,a	set 5,b	set 5,c	set 5,d	set 5,e	set 5,h	set 5,l	set 5,(hl)	set 5,a
F	set 6,b	set 6,c	set 6,d	set 6,e	set 6,h	set 6,l	set 6,(hl)	set 6,a	set 7,b	set 7,c	set 7,d	set 7,e	set 7,h	set 7,l	set 7,(hl)	set 7,a

xxIXxx (DD)

If the next byte is CB, it will follow xxIXBITxx, described later below. If the next byte is DD, ED, or FD, the current DD (the xxIXxx) will be ignored (functions like NOP).

Functions like the primary table, except each instance of hl is replaced with ix, h with ixh, and l with ixl, except in the case of (hl). (hl) will be replaced by (ix+x), where x is an 8-bit displacement, and all other h and l are unaffected. For example, ld ixh, (ix+x) is not an instruction, but ld h, (ix+x) is.

xxIYxx (FD)

Same as xxIXxx, but instead with IY, IYH, and IYL.

xxIXBITxx (DDCB)

Functions like xxBITxx, but instead applying the bitwise operations to (ix+x), then if the instruction wasn't BIT return the result to the register if it is not (hl). For example, rlc b becomes rlc (ix+x)->b.

xxIYBITxx (FDCB)

Same as xxIXBITxx, but instead with IY, IYH, and IYL.

Additional Information

Most of the instructions have more information here, or click on the instruction.

Source: Primary, xx80xx, xxBITxx: Xeda Elnara, aka Zeda xxIXxx, xxIYxx, xxIXBITxx, xxIYBITxx: www.z80.info/decoding.htm