<?xml version="1.0"?>
<feed xmlns="http://www.w3.org/2005/Atom" xml:lang="en">
	<id>http://learn.cemetech.net/index.php?action=history&amp;feed=atom&amp;title=Z80%3APorts</id>
	<title>Z80:Ports - Revision history</title>
	<link rel="self" type="application/atom+xml" href="http://learn.cemetech.net/index.php?action=history&amp;feed=atom&amp;title=Z80%3APorts"/>
	<link rel="alternate" type="text/html" href="http://learn.cemetech.net/index.php?title=Z80:Ports&amp;action=history"/>
	<updated>2026-06-16T08:33:51Z</updated>
	<subtitle>Revision history for this page on the wiki</subtitle>
	<generator>MediaWiki 1.43.3</generator>
	<entry>
		<id>http://learn.cemetech.net/index.php?title=Z80:Ports&amp;diff=338&amp;oldid=prev</id>
		<title>Maintenance script: Initial automated import</title>
		<link rel="alternate" type="text/html" href="http://learn.cemetech.net/index.php?title=Z80:Ports&amp;diff=338&amp;oldid=prev"/>
		<updated>2016-02-06T00:08:25Z</updated>

		<summary type="html">&lt;p&gt;Initial automated import&lt;/p&gt;
&lt;p&gt;&lt;b&gt;New page&lt;/b&gt;&lt;/p&gt;&lt;div&gt;&amp;#039;&amp;#039;&amp;#039;Note:&amp;#039;&amp;#039;&amp;#039; Until these pages are more fleshed out, see [http://wikiti.brandonw.net/?title=Category:83Plus:Ports:By_Address WikiTI:Ports By Name] for the appropriate information.&lt;br /&gt;
&lt;br /&gt;
Here&amp;#039;s a list of hardware ports and other related information concerning the ports. Note that the ports are addressed in &amp;#039;&amp;#039;&amp;#039;hexadecimal&amp;#039;&amp;#039;&amp;#039;. Some have common names, and some have no known use/do not exist at all.&lt;br /&gt;
&lt;br /&gt;
== Ports 00-0F ==&lt;br /&gt;
&lt;br /&gt;
* [[Z80:Ports:Port00|Port 00: Link]]&lt;br /&gt;
* [[Z80:Ports:Port01|Port 01: Keyboard]]&lt;br /&gt;
* [[Z80:Ports:Port02|Port 02: Status Port]]&lt;br /&gt;
* [[Z80:Ports:Port03|Port 03: Interrupt Mask]]&lt;br /&gt;
* [[Z80:Ports:Port04|Port 04: Memory Map / Interrupt]]&lt;br /&gt;
* [[Z80:Ports:Port05|Port 05: RAM Page(SE) - Port 16 Config/Link Assist (83+)]]&lt;br /&gt;
* [[Z80:Ports:Port06|Port 06: Memory Page A]]&lt;br /&gt;
* [[Z80:Ports:Port07|Port 07: Memory Page B]]&lt;br /&gt;
* [[Z80:Ports:Port08|Port 08: Link Assist Enable]]&lt;br /&gt;
* [[Z80:Ports:Port09|Port 09: Link Assist Status]]&lt;br /&gt;
* [[Z80:Ports:Port0A|Port 0A: Link assist Input Buffer]]&lt;br /&gt;
* [[Z80:Ports:Port0B|Port 0B: CPU Speed 2 Signaling Rate]]&lt;br /&gt;
* [[Z80:Ports:Port0C|Port 0C: CPU Speed 3 Signaling Rate]]&lt;br /&gt;
* [[Z80:Ports:Port0D|Port 0D: Link Assist Output Buffer]]&lt;br /&gt;
* [[Z80:Ports:Port0E|Port 0E: MemA High Flash Address]]&lt;br /&gt;
* [[Z80:Ports:Port0F|Port 0F: MemB High Flash Address]]&lt;br /&gt;
&lt;br /&gt;
== Ports 10-1F ==&lt;br /&gt;
&lt;br /&gt;
* [[Z80:Ports:Port10|Port 10: LCD Command/Status Port]]&lt;br /&gt;
* [[Z80:Ports:Port11|Port 11: LCD Data]]&lt;br /&gt;
* [[Z80:Ports:Port12|Port 12: LCD Command Mirror]]&lt;br /&gt;
* [[Z80:Ports:Port13|Port 13: LCD Data Mirror]]&lt;br /&gt;
* [[Z80:Ports:Port14|Port 14: Flash Control]]&lt;br /&gt;
* [[Z80:Ports:Port15|Port 15: ASIC Version]]&lt;br /&gt;
* [[Z80:Ports:Port16|Port 16: Flash Page Exclusion]]&lt;br /&gt;
* Port 17: SE Only, this always reads 0, and writing to it produces no apparent effect. It&amp;#039;s a bit suspicious, because all the ports before it and after it have a purpose. - WikiTI&lt;br /&gt;
* [[Z80:Ports:Port18/1F|Port 18-1F: MD5 Calculation]]&lt;br /&gt;
&lt;br /&gt;
== Ports 20-2F ==&lt;br /&gt;
TI-83+SE up only. For TI-83+, functions like 00-07.&lt;br /&gt;
* [[Z80:Ports:Port20|Port 20: CPU Speed Port]]&lt;br /&gt;
* [[Z80:Ports:Port21|Port 21: Hardware Type]]&lt;br /&gt;
* [[Z80:Ports:Port22|Port 22: Flash Lower Limit]]&lt;br /&gt;
* [[Z80:Ports:Port23|Port 23: Flash Upper Limit]]&lt;br /&gt;
* [[Z80:Ports:Port24|Port 24: Flash Execution Limits High Bit]]&lt;br /&gt;
* [[Z80:Ports:Port25|Port 25: RAM Execution Lower Limit]]&lt;br /&gt;
* [[Z80:Ports:Port26|Port 26: RAM Execution Upper Limit]]&lt;br /&gt;
* [[Z80:Ports:Port27|Port 27: Block Memory Mapping $C000]]&lt;br /&gt;
* [[Z80:Ports:Port28|Port 28: Block Memory Mapping 8000h]]&lt;br /&gt;
* [[Z80:Ports:Port29|Port 29: LCD Delay (6 MHz)]]&lt;br /&gt;
* [[Z80:Ports:Port2A|Port 2A: LCD Delay(15 MHz)]]&lt;br /&gt;
* [[Z80:Ports:Port2B|Port 2B: LCD Delay(15 MHz)(02)]]&lt;br /&gt;
* [[Z80:Ports:Port2C|Port 2C: LCD Delay(15 MHz)(03)]]&lt;br /&gt;
* [[Z80:Ports:Port2D|Port 2D: 32768Hz Crystal Control]]&lt;br /&gt;
* [[Z80:Ports:Port2E|Port 2E: Memory Access Delay]]&lt;br /&gt;
* [[Z80:Ports:Port2F|Port 2F: LCD Wait Delay]]&lt;br /&gt;
&lt;br /&gt;
== Ports 30-3F ==&lt;br /&gt;
TI-83+SE up only. For TI-83+, functions like 00-07.&lt;br /&gt;
* [[Z80:Ports:Port30/38|Port 30-38: Timers]]&lt;br /&gt;
* Port 38: Unknown&lt;br /&gt;
* [[Z80:Ports:Port39|Port 39: GPIO Configuration]]&lt;br /&gt;
* [[Z80:Ports:Port3A|Port 3A: GPIO Read/Write]]&lt;br /&gt;
* Port 3B: Very like does nothing. - WikiTI&lt;br /&gt;
* Port 3C: On DrDnar&amp;#039;s TI-84+CSE, these read 78, yet on a TI-84+SE with the TA3 ASIC, they read 00. - WikiTI&lt;br /&gt;
* Port 3D: Like 3C&lt;br /&gt;
* Port 3E: Like 3C&lt;br /&gt;
* Port 3F: Like 3C&lt;br /&gt;
&lt;br /&gt;
== Ports 40-4F ==&lt;br /&gt;
TI-83+SE up only. For TI-83+, functions like 00-07.&lt;br /&gt;
* [[Z80:Ports:Port40|Port 40: Clock Control]]&lt;br /&gt;
* [[Z80:Ports:Port41/44|Port 41-44: Clock Set]]&lt;br /&gt;
* [[Z80:Ports:Port45/48|Port 45-48: Clock Read]]&lt;br /&gt;
* Port 49: Unknown&lt;br /&gt;
* [[Z80:Ports:Port4A|Port 4A: D-Control]]&lt;br /&gt;
* Port 4B: Unknown&lt;br /&gt;
* [[Z80:Ports:Port4C|Port 4C: USB Controller Status]]&lt;br /&gt;
* [[Z80:Ports:Port4D|Port 4D: USB Line State]]&lt;br /&gt;
* Port 4E: Unknown&lt;br /&gt;
* Port 4F: Unknown&lt;br /&gt;
&lt;br /&gt;
== Ports 50-5F ==&lt;br /&gt;
TI-84+ up only. For TI-83+, functions like 00-07. TI-83+SE has no effect.&lt;br /&gt;
* Port 50: Unknown&lt;br /&gt;
* Port 51: Unknown&lt;br /&gt;
* Port 52: Unknown&lt;br /&gt;
* Port 53: Unknown&lt;br /&gt;
* [[Z80:Ports:Port54|Port 54: USB Controller Control]]&lt;br /&gt;
* [[Z80:Ports:Port55|Port 55: USB Interrupt State]]&lt;br /&gt;
* [[Z80:Ports:Port56|Port 56: USB Line Events]]&lt;br /&gt;
* [[Z80:Ports:Port57|Port 57: USB Line Event Mask]]&lt;br /&gt;
* Port 58: Unknown&lt;br /&gt;
* Port 59: Unknown&lt;br /&gt;
* [[Z80:Ports:Port5A|Port 5A: USB Presentation Link Port Mirroring Enable]]&lt;br /&gt;
* [[Z80:Ports:Port5B|Port 5B: USB Protocol Interrupt Enable]]&lt;br /&gt;
* Port 5C: Unknown&lt;br /&gt;
* Port 5D: Unknown&lt;br /&gt;
* Port 5E: Unknown&lt;br /&gt;
* Port 5F: Unknown&lt;br /&gt;
&lt;br /&gt;
== Ports 60-7F ==&lt;br /&gt;
* These are mirrors of ports 40-5F. They function the same as ports 40-5F.&lt;br /&gt;
&lt;br /&gt;
== Ports 80-8F ==&lt;br /&gt;
TI-84+/TI-84+SE only. On TI-83+, they function the same as 00-07. On TI-83, they have no effect.&lt;br /&gt;
* [[Z80:Ports:Port80|Port 80: USB Device Address]]&lt;br /&gt;
* Port 81: Unknown&lt;br /&gt;
* [[Z80:Ports:Port82|Port 82: USB Write Pipe-Events]]&lt;br /&gt;
* [[Z80:Ports:Port83|Port 83: USB Write Pipe-Events (cont.)]]&lt;br /&gt;
* [[Z80:Ports:Port84|Port 84: USB Read Pipe-Events]]&lt;br /&gt;
* [[Z80:Ports:Port85|Port 85: USB Read Pipe-Events (cont.)]]&lt;br /&gt;
* [[Z80:Ports:Port86|Port 86: USB Miscellaneous Events]]&lt;br /&gt;
* [[Z80:Ports:Port87|Port 87: USB Output-Enabled Pipes]]&lt;br /&gt;
* [[Z80:Ports:Port88|Port 88: USB Output-Enabled Pipes (cont.)]]&lt;br /&gt;
* [[Z80:Ports:Port89|Port 89: USB Input-Enabled Pipes]]&lt;br /&gt;
* [[Z80:Ports:Port8A|Port 8A: USB Input-Enabled Pipes (cont.)]]&lt;br /&gt;
* [[Z80:Ports:Port8B|Port 8B: USB Events Mask]]&lt;br /&gt;
* [[Z80:Ports:Port8C/8D|Port 8C-8D: USB Frame Counter]]&lt;br /&gt;
* [[Z80:Ports:Port8E|Port 8E: USB Pipe Number]]&lt;br /&gt;
* [[Z80:Ports:Port8F|Port 8F: VBus Control]]&lt;br /&gt;
&lt;br /&gt;
== Ports 90-9F ==&lt;br /&gt;
TI-84+/TI-84+SE only. On TI-83+, they function the same as 00-07. On TI-83, they have no effect.&lt;br /&gt;
* [[Z80:Ports:Port90|Port 90: USB Write Packet Size]]&lt;br /&gt;
* [[Z80:Ports:Port91|Port 91: USB Write Command/Status]]&lt;br /&gt;
* Port 92: Unknown&lt;br /&gt;
* [[Z80:Ports:Port93|Port 93: USB Read Packet Size]]&lt;br /&gt;
* Port 94: Unknown&lt;br /&gt;
* Port 95: Unknown&lt;br /&gt;
* [[Z80:Ports:Port96|Port 96: USB Data-Received Counter]]&lt;br /&gt;
* Port 97: Unknown&lt;br /&gt;
* [[Z80:Ports:Port98|Port 98: USB Write-Endpoint Type/Address]]&lt;br /&gt;
* Port 99: Unknown&lt;br /&gt;
* [[Z80:Ports:Port9A|Port 9A: USB Read-Endpoint Type/Address]]&lt;br /&gt;
* Port 9B: Unknown&lt;br /&gt;
* Port 9C: Unknown&lt;br /&gt;
* Port 9D: Unknown&lt;br /&gt;
* Port 9E: Unknown&lt;br /&gt;
* Port 9F: Unknown&lt;br /&gt;
&lt;br /&gt;
Information Taken from [http://wikiti.brandonw.net/?title=Category:83Plus:Ports:By_Address WikiTI:Ports By Address].&lt;br /&gt;
&lt;br /&gt;
------&lt;br /&gt;
&lt;br /&gt;
{{lowercase}}&lt;br /&gt;
[[Category:Z80 Assembly]]&lt;br /&gt;
[[Category:Z80 Heaven]]&lt;br /&gt;
[[Category:Z80 Ports]]&lt;/div&gt;</summary>
		<author><name>Maintenance script</name></author>
	</entry>
</feed>